What is CMOS? Working Principle & Its Applications

Table Of Content

What is CMOS Logic Family?

Let’s assume a Complementary Metal Oxide Semiconductor inverter circuit consists of p-type and n-type MOSFET. Input A will serve as the gate voltage for both transistors.

The NMOS transistor will receive input from Vss (ground), while the PMOS transistor will receive input from Vdd. For output, the Y terminal will be used. When a high voltage (~ Vdd) is applied to the inverter’s input terminal (A), the PMOS opens and the NMOS switches off, causing the output to be pushed down to Vss.

When a low voltage (<Vdd, ~0v) is provided to the inverter, the NMOS turns off, and the PMOS turns on. So, the output becomes Vdd, or the circuit is brought up to Vdd.

Input	Logic Input	Output	Logic Output
0v	0	Vdd	1
Vdd	1	0v	0

What is CMOS NAND Gate

Suppose there’s a 2-input CMOS NAND gate consisting of two series NMOS transistors between Y and Ground and two parallel PMOS transistors between Y and VDD.

If either input A or B is logic 0, at least one of the NMOS transistors will be turned off, interrupting the flow from Y to Ground. However, at least one of the pMOS transistors will be active, forming a channel from Y to VDD.

Thus, the Y output will be high. If both the inputs are high both NMOS transistors will be ON and both the PMOS transistors will be OFF. Consequently, the output will be low. The truth table of the NAND gate is shown in the following table.